1. Field of the Invention
The present invention relates to a manufacturing method of a liquid crystal display device using a crystalline semiconductor film formed by crystallizing an amorphous semiconductor film including silicon, and more particularly, to a manufacturing method of an active matrix substrate with a thin film transistor (TFT) formed on the substrate.
2. Description of the Related Art
Recently, lowering of the temperature in a semiconductor manufacturing process is advancing. The important reason is that there is a need to form a TFT on an insulating substrate such as glass, which is cheap and has high processability. Further, in the semiconductor manufacturing process, it is necessary to crystallize amorphous components contained in a semiconductor material or an amorphous semiconductor material, or to improve crystallinity for high operation speed of the TFT.
A technique for obtaining a crystalline silicon film on a glass substrate is already disclosed as described in Japanese Patent Application Laid-open No. Hei 7-130652. This is a technique of adding a catalyst element which promotes crystallization to an amorphous silicon film and forming the crystalline silicon film by conducting a heating process.
This technique enables lowering of the crystallization temperature of the amorphous silicon film by 50 to 100xc2x0 C. by the action of the catalyst element, and reducing of the time required for crystallization by ⅕ to {fraction (1/10)}. Further, it is experimentally confirmed that the crystalline silicon film obtained by the technique has an excellent crystallinity.
However, the metal element such as nickel or cobalt used as the catalyst element, forms a deep level in the silicon film to thereby capture a carrier, so that in a case a TFT is manufactured using the obtained crystalline silicon film, it is confirmed that the catalyst element in the active layer of the TFT will segregate irregularly. If the segregated portion is in a channel region (a region where channels are formed) or a high resistant region (for example, a portion which is called an offset region) of a TFT, it becomes a leak path for weak current, and may become a cause of sudden increase of an off current (a current when the TFT is in an off state).
Accordingly, after crystallization, it is preferable that the catalyst element is removed promptly, or reduced to a degree that it does not cause electrical influence. As a means for this, a technique of using the gettering effect may be used.
A technique for removing or reducing the catalyst element by gettering is disclosed in, for example, Japanese Patent Application Laid-open Hei No. 11-54760. In the technique described in Embodiments 1 and 2 in the publication, a gettering region 302 which includes phosphorus and captures the catalyst element (hereinafter referred to as a gettering sink) is provided near the TFT, and this is removed after the catalyst element is gettered.
In this method, the gettering region 302 is provided in the periphery of the TFT semiconductor layer so that the patterning margin is large. On the other hand, there is a problem in that the area efficiency of the semiconductor layer constituting the TFT lowers and the improvement of the accumulation becomes difficult.
On the other hand, the technique in Embodiments 3, 4 and 5 makes a source region and a drain region function as a gettering sink to improve the accumulation.
As shown in FIG. 4, this method is one of providing gettering sinks 403 to 406 in a self-aligning manner with gate wirings 409 and 410 as masks, and there is no need to provide a gettering sink on the outside of regions of TFT 411 or 412, and the area efficiency is not lowered. However, since a large amount of phosphorus for gettering is doped in the source region 403 and the drain region 405 of the p-channel TFT 411, a larger amount of boron needs to be doped in the source region 403 and the drain region 405 for forming the p-type semiconductor.
Therefore, there was also a problem of lowering of throughput in the doping step, or of improvement of crystallinity of the source region and the drain region becoming difficult. The doping for imparting the p-type conductivity for carrier inversion with respect to the region that has been doped by imparting the n-type conductivity is called cross doping or counter doping.
As described above, the gettering process of removing the catalyst element from the channel region is an effective process when manufacturing a TFT using the crystalline silicon film. Therefore, the need to efficiently perform the gettering process is increasing.
If the gettering sink is provided in the periphery of the TFT, the area efficiency is lowered and the accumulation of the TFT cannot be raised. A first object of the invention is to getter the catalyst element of the channel region without lowering the area efficiency of the semiconductor layer.
Further, when cross doping is conducted in the source region or the drain region of the p-channel TFT for forming a gettering site, the throughput of the doping process is lowered. A second object of the invention is to getter the catalyst element in the channel region without lowering the throughput in the doping process.
Then, by solving both the above first and second objects, a highly reliable liquid crystal display device with high productivity in which the catalyst element is efficiently gettered from the channel region, and the accumulation of TFT is high can be manufactured. Further, at the same time, it is an object to improve the quality and reliability of electrical equipment using the liquid crystal display device, by manufacturing the liquid crystal display device in accordance with the present invention.
In order to solve the above object, the inventors of the present invention considered gettering the catalyst element included in the active layer by a gettering sink provided on the outer side of the TFT region in the p-channel TFT. The TFT region referred to here indicates the region occupied by the source region, the drain region, and the channel region.
If the gettering sink is provided on the outer side of the TFT region, there is no need to conduct cross doping and throughput of the doping process is improved. However, at the same time, by providing the gettering sink on the outer side of the TFT region, a problem in that the area efficiency of the active layer is lowered occurs as described above.
The present inventors considered combining the steps of providing a gettering sink on the outside of the p-channel TFT region, and removing the region provided on the outside of the TFT region in a self-aligning manner by a source wiring or a drain wiring, out of the regions where the catalyst element was performed with gettering. By removing the gettering sink in a self-aligning manner, the alignment margin for patterning is not necessary, so that gettering may be performed without lowering the area efficiency.
As described above, the object of the present invention is to efficiently getter the catalyst element from the inside of the film to the crystalline silicon film crystallized by using the catalyst element, and specifically the present invention relates to the step of selectively adding the element that belongs to the periodic table group 15 and conducting the heating process. The heating process is conducted by furnace annealing (heating process in the electric furnace), and may use heating means such as laser annealing or lamp annealing.
As a catalyst element promoting crystallization, there is used an element, which is selected from the group consisting of Ni (nickel), Co (cobalt), Fe (iron), Pd (palladium), Pt (platinum), Cu (copper) and Au (gold). In the experiment of the present applicant, the most suitable element is determined to be nickel.
Further, in the present invention, the periodic table group 15 elements added when the gettering sink is formed are N (nitrogen), P (phosphorus), As (arsenic), Sb (stibium), and Bi (bismuth), and it is known that phosphorus shows a particularly significant effect, with arsenic following.